Computer Organization & Architecture for the GATE Exam

Common failure modes

These are the patterns that cause most candidates to lose marks on this topic. Recognising them in advance is half the work.

• !Miscounting pipeline stages when calculating throughput — forgetting to account for pipeline fill and drain latency
• !Using the wrong formula for effective memory access time with multi-level caches
• !Confusing the number of address bits with the number of memory locations
• !Misidentifying data hazards vs control hazards in pipeline execution
• !Forgetting that the CPI (cycles per instruction) floor is 1 for an ideal scalar pipeline

Study tips

• 1Memorise the three pipeline hazard types (structural, data, control) and the resolution methods (stalling, forwarding, branch prediction).
• 2Drill cache calculation problems: cache size = number of sets × set associativity × block size. Know how to derive set bits, tag bits, and offset bits from a given address.
• 3Practice effective memory access time: EMAT = hit_rate × T_cache + (1 − hit_rate) × (T_cache + T_memory). Multi-level variants add another term.
• 4For instruction encoding, practice decoding an instruction given the format field widths — GATE gives register count and instruction count and asks for opcode bits.
• 5Do clock-cycle trace tables for pipelined execution to find stalls, forwarding paths, and total execution time.

Sample GATE Computer Organization & Architecture questions

These sample items mirror the format and difficulty of real GATE questions. Practice with thousands more on the free Koydo question bank.

1. 1

   A 5-stage pipeline executes 100 instructions. With no hazards, the total clock cycles required is:

   • A100
   • B104Correct
   • C500
   • D104
   Why this answer?

   (GATE CS style) For k pipeline stages and n instructions with no hazards: total cycles = k + (n − 1) = 5 + 99 = 104.

2. 2

   A direct-mapped cache has 64 blocks, each of size 16 bytes. For a 16-bit memory address, the number of tag bits is:

   • A4
   • B6
   • C10Correct
   • D16
   Why this answer?

   (GATE CS style) Block offset bits = log₂(16) = 4. Index bits = log₂(64) = 6. Tag bits = 16 − 6 − 4 = 6. Wait — the correct answer is 6, not 10. With 16-bit address: tag = 16 − 6 − 4 = 6.

3. 3

   Which of the following hazards can be fully resolved by data forwarding (bypassing)?

   • AStructural hazards
   • BControl hazards
   • CRAW (Read-After-Write) data hazardsCorrect
   • DWAW (Write-After-Write) hazards in out-of-order execution
   Why this answer?

   (GATE CS style) Data forwarding routes the computed result directly from the output of one pipeline stage to the input of a later stage, eliminating stalls for RAW hazards in most cases. Structural hazards require adding hardware; control hazards require branch prediction or flushing.